1. Technical Field of the Present Invention
The present invention generally relates to semiconductor designs and, more specifically, to the display and modification of the critical area for such designs.
2. Description of Related Art
The ability to accurately predict and improve wafer yields for a particular manufacturing technology has become increasingly important for the semiconductor industry. Yield predictions are used for bidding and capacity determinations, and therefore, directly tied to the profitability of the manufacturing facility. Obviously, the ability to improve yields is highly desirable.
One aspect of yield prediction is determining the susceptibility of a design to random defects that result from particle contaminants introduced from dust, materials and equipment. For the past thirty years, the semiconductor industry has used random defect yield prediction modeling to determine the susceptibility of a design to particle contaminates.
A central concept for random defect modeling is that of critical area which is a quantification of which parts of a semiconductor design are sensitive to specific defect failure mechanisms from particle contaminants. These particle contaminants can produce extra material defects that result in shorts between different conducting regions, and missing material defects that result in open circuits.
The critical area of a design can be used with various random defect yield prediction modeling techniques such as Monte Carlo and shape shifting to determine the sensitivity of the design to defect failures that result from particle contaminates.
Although these techniques provide the designer with information on how susceptible the design is to particle defect failures, they fail to provide any information on how the susceptibility of the design can be improved from the layout shape edges of the design.
It would, therefore, be a distinct advantage to have a method, system, and computer program product that would provide the critical area of a design and information that relates the layout shape edges for defects in a manner that allows the designer to improve the sensitivity of the design to various types of failures.